0622 실습 2-1~2-4

데이터플로우 모델링으로 1차실습때의 내용을 재구성함

1번,2번 4:1MUX 두가지방법, 3번 fulladder

4,5번은 새로나온 문제로 직접 설계해야했다

4번 decoder , 5번 비교기 comparator

 

 

2-1, 2-2

module MUX4_to_1 (
	output wire out,
	input  wire I0, I1, I2, I3,
	input  wire S1, S0
);

 assign out = (~S1 & ~S0 & I0) | (~S1 & S0 & I1) | (S1 & S0 & I3);

endmodule



module MUX4_to_1_two (
	output wire out,
	input  wire I0, I1, I2, I3,
	input  wire S1, S0
);

 assign out = S1 ? (S0 ? I3 : I2) : (S0 ? I1 : I0);

endmodule

 

2-2

module fulladd4 (
 output wire [3:0] SUM,
 output wire       C_OUT,
 input  wire [3:0] X,Y,
 input  wire       C_IN
);

 assign {C_OUT, SUM} = X + Y + C_IN;

endmodule

 

2-5 decoder

module DEC2_to_4 (
 output wire [3:0] Dout,
 input  wire [1:0] Din,
 input  wire       Enable
);
 
 assign Dout = (Dout && Enable) ? (4'b0001 << Din) : 0;

endmodule

2-5 tb_decoder

`timescale 10ns/1ps
module tb_dec;

wire [3:0] Dout;
reg  [1:0] Din;
reg  Enable;


 // Form : module DEC2_to_4 ([3:0] Dout,[1:0] Din,Enable);
 DEC2_to_4 mydec (
	.Dout (Dout),
	.Din  (Din),
	.Enable (Enable)
 );

 initial 
 begin
    Enable = 0; Din = 2'b01;
 #1 Enable = 0; Din = 2'b00;
 #1 Enable = 1; Din = 2'b01;
 #1 Enable = 0; Din = 2'b01;
 #1 Enable = 1; Din = 2'b11;
 #5;  // why comment
 end

endmodule

 

2-4 comparator

module comparator4 (
 output wire GT,
 output wire EQ,
 output wire LT,
 input  wire [3:0] A,
 input  wire [3:0] B,
 input  Enable
 );
/*
 assign GT = ((A>B)  & Enable)  ? 1 : 0;
 assign EQ = ((A==B) & Enable)  ? 1 : 0;
 assign LT = ((A<B)  & Enable)  ? 1 : 0;
*/
 assign GT = ((A>B)  && Enable)  ? 1 : 0;
 assign EQ = ((A==B) && Enable)  ? 1 : 0;
 assign LT = ((A<B)  && Enable)  ? 1 : 0;

// ues operator &, &&
  
endmodule

2-4 tb_comparator

`timescale 10ns/1ps
module tb_comparator4;

wire GT, EQ, LT;
reg  [3:0] A;
reg  [3:0] B;
reg  Enable;

// Form :module comparator4 (GT,EQ, LT, [3:0] A, [3:0] B, Enable)
comparator4 my_comparator (GT, EQ, LT, A, B, Enable);

 initial begin
 	    A = 4'b0000; B=4'b0000; Enable = 1'b0;
	#1  A = 4'b0000; B=4'b0001; Enable = 1'b0;
	#1  A = 4'b0001; B=4'b0001; Enable = 1'b1;
	#1  A = 4'b0110; B=4'b0011; Enable = 1'b1;
	#1  A = 4'b1000; B=4'b0000; Enable = 1'b1;
	#1  A = 4'b0000; B=4'b0000; Enable = 1'b0;
	#1  A = 4'b0011; B=4'b0001; Enable = 1'b1;
	#1  A = 4'b1000; B=4'b1000; Enable = 1'b1;
	#1  A = 4'b0101; B=4'b1100; Enable = 1'b1;
	#5;
end

endmodule