0623 실습 3-1~3-3

동작적 행위 모델링으로 mux, counter, alu8function 작성해봄

 

동작적 행위 모델링 형태

always @(신호리스트)
begin
  // 내부에 case문 작성 가능
  case (x)
	1 : x가 1일때의 동작;
	0 : x가 0일때의 동작;
  endcase
end

 

3-1  4:1mux

module MUX4_to_1 (
	output reg OUT,
	input  wire I0, I1, I2, I3,
	input  wire S1, S0
);

 always @ (S1 or S0 or I0 or I1 or I2 or I3)
	case ({S1, S0})
	 2'd0: OUT=I0;
	 2'd1: OUT=I1;
	 2'd2: OUT=I2;
	 2'd3: OUT=I3;
	 default : $display("Invalid control signals");
	endcase

endmodule

 

tb_mux

`timescale 10ns/1ps

module tb_mux;

reg IN0, IN1, IN2, IN3;
reg S0, S1;
wire OUTPUT;

MUX4_to_1 behavior_mux( OUTPUT, IN0, IN1, IN2, IN3, S1, S0);

initial
begin
	IN0 = 1'b0; IN1 = 1'b0; IN2 = 1'b1; IN3 = 1'b1;
	S1 = 1'b0; S0 = 1'b0;
	# 1
	S1 = 1'b0; S0 = 1'b1; 
	# 1
	S1 = 1'b1; S0 = 1'b0;  
	# 1
	S1 = 1'b1; S0 = 1'b1; 
	# 1;
end

endmodule

 

 

3-2 counter

module Counter4 (
	output reg [3:0] Q,
	input wire clk,
	input wire clr
);

always @(posedge clk)
begin
	if (!clr) Q = 4'b0000;  // if clear == 0 or Q == 4'b1111
	else Q = Q + 1'b1;
end

endmodule

 

 

tb_counter

`timescale 10ns/1ps
module tb_counter;

wire [3:0] Q;
reg CLK;
reg CLR;

// module :  Counter4 ([3:0] Q, clk, clr);
Counter4 behavior_counter (
	.Q   (Q),
	.clk (CLK),
	.clr (CLR)
);

//Counter4 behavior_counter(Q, CLK, CLR);

initial begin
CLK = 1'b0; CLR = 1'b0;
#3 CLR = 1'b1;
#20 $finish;
end

always begin
#1 CLK = ~CLK;
end

endmodule

 

 

3-3 ALU8function

module ALU_8func (
	output reg [3:0] OUT,
	input  wire [3:0] IN0,
	input  wire [3:0] IN1,
	input  wire [2:0] SEL
);

always @(*)
begin
	case (SEL)
	3'b000 : OUT = IN0;
	3'b001 : OUT = IN0 + IN1;
	3'b010 : OUT = IN0 - IN1;
	3'b011 : OUT = IN0 / IN1;
	3'b100 : OUT = IN0 % IN1;
	3'b101 : OUT = IN0 << 1;
	3'b110 : OUT = IN0 >> 1;
	3'b111 : OUT = (IN0>IN1);
	default : OUT = 1'bx;	
	endcase
end

endmodule

 

 

tb_ALU_8func

`timescale 10ns/1ps

module tb_ALU_8func;

wire [3:0] OUT;
reg  [3:0] IN0;
reg  [3:0] IN1;
reg [2:0] SEL;

ALU_8func beh_ALU (
	.OUT (OUT),
	.IN0 (IN0),
	.IN1 (IN1),
	.SEL (SEL)
);

initial begin
IN0 =4'b0101; IN1 = 4'b0010;
SEL = 3'b000;
#10 $finish;
end


always begin
#1 SEL = SEL + 1'b1;
//if (SEL < 3'b111) SEL = SEL + 1'b1;
//if (SEL == 3'b111) SEL = 3'b000;
end


endmodule