0621 FullAdder 바텀업 설계 (실습 1-1~1-4)
MUX4_to_1 4:1 멀티플렉서 s1s0신호에 따라서 y0~y3의 신호가 출려됨 module MUX4_to_1( output wire OUT, input wire I0, I1, I2, I3, input wire S1, S0 ); wire s1n, s0n; wire y0, y1, y2, y3; not (s1n, S1); not (s0n, S0); and (y0, I0, s1n, s0n); and (y1, I1, s1n, S0); and (y2, I2, S1, s0n); and (y3, I3, S1, S0); or (OUT, y0, y1, y2, y3); endmodule tb_mux `timescale 10ns/1ps module tb_mux; reg IN0, IN1, IN2, IN3; reg S0, ..